Testing A / D Converters – Course Syllabus

Conversion Basics

Digital vs. Analog Testing
Mixed Signal Testing
Converter Test Overview
Verifying Converter Performance
Static Testing
Dynamic Testing

ATE Architectures for ADC Test

Traditional Linear ATE Architectures
ATE Mixed Signal Architectures
Waveform Generator Overview
Waveform Generator Memory and Conversion
Waveform Generator Conditioning and Filtering
Waveform Digitizer Overview
Waveform Digitizer Conditioning and Filtering
Waveform Digitizer Capturing, Converting, and Storing
Digital Signal Capture
Digital Signal Processor
DSP Library

ADC Theory of Operation

High Bandwidth Analog Input
Quantization Error
Latched or Buffered Outputs
Serial or Parallel Outputs
ADC Block Diagram
Five Different ADC Architectures
ADC Technologies
Flash Example
Flash Advantages & Disadvantages
Successive Approximation (SAR)
SAR Example
SAR Advantages & Disadvantages
Subranging (Pipelined)
Subranging Advantages & Disadvantages
Integrator Timing
Integrating Advantages & Disadvantages
Sigma-Delta Advantages & Disadvantages

ADC Static Testing

ADC Static Terminology
Transition Voltages (VT)
Code Width (CW)
Code Width of First and Last Codes
Full Scale Transition Range (FSTR)
LSBDUT Calculation
Full Scale Range
ADC Static Specifications
Offset Voltage and Offset Error
Gain Voltage and Gain Error
Differential nonlinearity (DNL)
DNL Example
No missing codes
Integral nonlinearity (INL)
“Center of Code”
INL Example – Code Centers
INL Example – Summation
Comparison of INL Techniques
Which is Best?
Summary of ADC Static Specifications
ATE Configuration for Static Test
Example ADC Static Specification
Parameter Measurement Requirements
Which Codes to test?
How to Test ADC Static Specs
Five Steps to Success With Static Tests
Providing an Accurate Vref
Providing an Accurate Vin
Digital Stimulus
Digital Capture
Analysis Routines for Calculating Static Test Results
Servo Loop Transition Voltages
AWG Ramp Transition Voltages
Test Implications
Calculating Histogram Parameters
Input Signal Overdrive
Average Hits per Code – Example
Histogram Example
Getting Gain and Offset from a Histogram
Problems with Histograms
Segmented Ramp Technique
Architecture-Specific Test Considerations
Flash Test Considerations
SAR Test Considerations
Subranging Test Considerations
Integrating Test Considerations
Sigma-Delta Test Considerations
Test Considerations Summary
Static Testing Key Points

ADC Dynamic Parameters

ADC Dynamic Testing
Signal Classification
Harmonic Distortion
Frequency Domain Analysis
Distortion in the Frequency Domain
Total Harmonic Distortion
Gaussian Noise
Quantization Noise
Correlated Noise
Noise in the Frequency Domain
Signal-to-Noise Ratio
Superposition in Linear Systems
Intermodulation Distortion
IM in the Frequency Domain
Intermodulation Distortion Testing
Dynamic Range
Spurs in the Frequency Domain
Spurious Free Dynamic Range
Testing ADC Dynamic Parameters
Test System Configuration
Example ADC Dynamic Specification
Parameter Measurement Requirements
Dynamic Test Checklist
AWG Coherent Sine
Reconstruction Filtering
Purifying Filter
Scaling the Input Signal
Level Shifting
Buffering the ADC Input
Sampling Parameters for the Input Signal
Coherent Sampling Example
Digital Capture Instrument
Analysis of Captured Data
Other Dynamic Test Considerations
Undersampling Equation
Undersampling Example
Sparkle Codes
Sine Histograms
Sine PDF Math
Sine Histogram Scaling to DUT
Effective Number of Bits (ENOB)
Effect of Jitter on ADC Results
ADC Jitter Example

Dynamic Testing – Key Points

Summary – Questions and Answers

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