This text focuses on the Fundamentals of Memory Component Test using ATE. It is intended for use by Test, Product and Applications Engineers. The material addresses the issues of algorithmic patterns and their use for fault detection within memory devices. The ability of each unique pattern to detect Specific Fault Types and the advantages and disadvantages associated with each pattern are discussed.
To simplify the complexities associated with various Algorithmic Test Patterns, a Static RAM is used as the primary test circuit, the concepts presented however apply to many types of memory devices.
The following information accompanies the explanation of each algorithmic pattern:
- A flow chart
- Sample code used to generate the pattern
- Graphics to illustrate the relationship between address and data
- The unique fault coverage
- A formula for calculating the pattern’s execution time
The Architecture and Performance Specifications of a typical Memory Test System are presented, including the following subjects:
- Topological scrambling (address and data)
- Error catch (as used for Bitmaps and Redundancy Repair and Analysis)
- Clocked high voltage levels – VIHH & VBUMP
- Stored patterns – the memory version of vectors
- Timers and their use
- Parallel test
A CD-ROM of animated graphics is also included to illustrate the relationship of data vs. address. These illustrations provide a visual reference to help you understand the pattern sequences at the most fundamental level.
Embedded memories are now included in a growing number of digital and mixed signal devices. The pattern information contained in this text is designed to jump start your understanding of memory test, and provide a fundamental understanding of pattern functionality.