Test and Product Engineers often work with Design for Test (DFT) enabled chip designs without a clear understanding of the embedded Design for Test circuitry or the functions of the Test Vector Patterns. This text presents an overview of common DFT logic, DFT test issues, and methods of Test Vector Generation. Introductions to Simulation, Fault Models, and Automatic Test Pattern Generation (ATPG) are also included.The text consists of two main topics: Design for Test Circuitry and Simulation/Vector Generation. DFT is addressed first, then simulation and test vector generation follows.
Details of Scan circuitry, Scan test conditions, and Scan Vector patterns are explained. Boundary Scan (JTAG IEEE1149.1) is also covered in a similar manner. Built In Self Test (BIST) is discussed along with common elements of BIST such as On-Board Pattern Generators (LSFR), and Output Compactors (MISR). The use of IOBIST for basic test verification of IO circuits is discussed as well as Reduced Pin Count Testing (RPCT).
Simulations run on circuit models are often the source of digital test vector patterns. Circuits are modeled using a Hardware Description Language (HDL) such as Verilog® or VHDL, so a number of these examples are included. Examples of data produced by simulation are explained and the final discussion addresses translating simulation data to the target test system’s vector format.
To see more click Table of Contents