Memory Testing – Course Syllabus

Introductions

An SRAM block diagram
Cell
SRAM is often a Flip-Flop

Array
Stuck At Fault/ What is it?
How does it happen?
What will it look like to the end user?
Under a SEM
Coupling Fault
Neighborhood Pattern Sensitive Fault

Addressing
Row decoders
Column decoders
Addressing Fault

Data in/out
Output buffers
Sense amps
Transition Fault

Control signals
Chip Enable
Stand-by power levels on SRAM
Output enable
Write enable
Truth table from data sheet

Patterns
Checkerboard
Slides / Faults / Micro-code Examples / Test times
Address complement
Slides / Faults / Micro-code Examples / Test times
March
Slides / Faults / Micro-code Examples / Test times
Read Modify Write timing and pattern
Slides / Faults / Micro-code Examples / Test times
March C
Slides / Faults / Micro-code Examples / Test times
How is this different from March?
Where and why would it be used?
Matts++
Slides / Faults / Micro-code Examples / Test times
How is this different from March?
Where and why would it be used?
Sliding diagonal
Slides / Faults / Micro-code Examples / Test times
Where and why would it be used?

Memory testers and options

Vectors and Micro-code

APG

Data Generator

Topological scrambling
Address
What is topo scram on DUT?
What is scramble ram on tester?
What patterns would this affect?
Data

Timer(s)
Refresh
Failure to program

Error catch ram
Redundancy and repair
Bitmap
Data RAM
Vector type storage
ROM’s and OTP’s
User library

VIHH
Special modes
Programming of NVM’s
Software write protection in E2prom’s
Vbump
How and Why

Parallel testing
Resources per pin/site/tester
Resources (some are options!) required per device to be tested
DPS
APG
ECR
Data Ram

Additional patterns – How and Why
Walking 0/1’s
Slides / Faults / Test times
Galpat
Slides / Faults / Test times
Butterfly
Slides / Faults / Test times
Surround Disturb
Slides / Faults / Test times
Moving Inversion
Slides / Faults / Test times

Class Summary

Q & A

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