Digital Testing Knowledge Evaluation

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Print this and answer the questions below. If you miss more than 3, then you are a good candidate for this course.

Match the terms with the definitions below

A: NegativeB: StaticC: VREF/VCOM

D: IDD or ICC

E: IOH

F: Preconditioning

G: Dynamic

H: VIL

I: Binning

J: Hold Time

K: Boundary Scan

L: Setup Time

M: Pin Electronics

N: ComparatorsO: Wafer TestP: VOL

Q: IOL

R: VDDMAX

S: Positive

T: Defect

U: Fault Coverage

V: DPM

W: Fault

X: DFT

Y: Bi-directional or IO

1. The parameter that defines the acceptable power supply current of a semiconductor device.

2. This term indicates that the device under test is actively changing logic states.

3. The AC parameter that defines the minimum amount of time that data must be held after a reference signal reaches a certain voltage point.

4. A device pin that functions as an input, an output and is also capable of achieving a high impedance state.

5. A term used to describe logic that is added to a circuit design to improve its testability.

6. A means of categorizing or sorting tested devices into their appropriate groupings

7. The parameter that defines the minimum current that an output must source when driving a logic one.

8. Circuitry located in the test head used to supply input signals to the device under test and to
receive output signals from the device under test.

9. The reference voltage associated with the dynamic current loads, used to control the switching point of IOL and IOH currents.

10. The parameter that defines the maximum voltage which may be applied to an input pin when applying a logic zero

11. A physical flaw introduced into a circuit during the manufacturing process.

12. The polarity of current when flowing into the test system.

13. A measure of the effectiveness of a vector test pattern.

14. The polarity of current supplied by the test system during an IOL test

15. The name of the IEEE 1149.1 standard

Select the correct answer for the questions below

16. The VIL/VIH specifications are verified by executing:
a. A DC test
b. A functional test
c. Only verified through Failure Analysis
d. No test, these parameters are guaranteed by design

17. Propagation measurements are only made at outputs:
a. True
b. False

18. When performing a functional opens and shorts test, the current is forced by:
a. The PMU
b. The programmable current loads
c. Voltage is normally forced, not current
d. None of the above

19. A linear search typically executes slower than a binary search
a. True
b. False

20. When Performing the VOH test, the current forced during the test is:
a. A positive current
b. A negative current
c. a or b

21. The IIL/IIH test verifies:
a. Input capacitance
b. Input threshold levels
c. Input impedance

22. When the device specifications defines VDD as 3.0V +/- 5%, the value of VDDMIN is:
a. 3.15 volts
b. 3.25olts
c. 2.85 volts
d. It depends on the technology

23. Open drain outputs do not have the ability to:
a. Drive a logic 0
b. Drive a logic 1
c. Source current
d. B and C

24 The output enable parameter tests the transition time of an output changing from driving valid logic levels to a high impedance state.
a. True
b. False

25. The first testing to take place on a new circuit design is often called:
a. Quality Assurance Test
b. Design Validation
c. Class Test
d. Incoming Inspection

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