This course is designed to explain the concepts and techniques associated with testing DFT enabled digital circuits. The information presented is founded upon DFT theory, but is also practical, relating directly to test problems, test programs and test equipment. The information presented will enable you to better understand how the various tests are implemented and how to verify and trouble-shoot problems.
Our goal is to provide useful information that will quickly improve the skill set required to be a productive digital DFT Test or Product Engineer. We present an environment where questions and interactions are welcomed and everyone is treated with respect regardless of their experience level.
- Introduction to DFT and current test issues
- Fault Models
- Automatic Test Pattern Generation (ATPG)
- DFT Details
- DC and AC Logic Scan
- Boundary Scan IEEE 1149.1 JTAG
- Built-In Self Test – Vector Compression – Iddq
- IO BIST and Reduced Pin Count Test
- DFT Focused ATE
- Distribution Materials
- Handout of course slides and all classroom materials are provided with the course
Students should have completed the Soft Test Digital Test Technology class or have equivalent experience.