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DFT Fundamentals - 1-Day Overview T Today’s
Test and Product Engineers are regularly involved with DFT enabled chip
designs, but the details of DFT test methodologies often remain a mystery.
Design for Testability courses have been offered in the past, but most focus
primarily on circuit design – not Test. This course has been developed
specifically for engineers involved with component test of digital IC’s. Fault Models, ATPG, Structural Test, Reduced Pin Count Test and Iddq are just some of the topics covered. The course material will enhance your current knowledge and you will likely find that you can put into practice what you learn immediately. This DFT Fundamentals Course is designed to provide a foundation of knowledge that will enable you to take full advantage of the benefits associated with DFT technology. The
Course DC and AC Scan are explained in detail, including DFT Structures, Test Strategies, and Timing Sequences. Boundary Scan 1149.1 (JTAG) is explained in similar detail, followed by an in-depth discussion of Built-In Self Test (BIST) for Memory and Logic circuits. The procedures and benefits of Reduced Pin Count Test are explored along with IOBIST. The course concludes with a comparison of DFT ATE to more traditional ATE. For more details of what is included in the course, please see the attached Course Syllabus. Who should attend When, Where
& Cost
Class Registration
Summary
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2007 | Soft Test, Inc. | All Rights Reserved |
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