DFT Fundamentals Knowledge Evaluation
Take the Challenge!

Print this and answer the questions below. If you miss more than 3, then you are a good candidate for this course.

Click here for a printable version.

Match the terms with the definitions below

1. The term that describes the behavior of a defective circuit based upon a specific type of defect

2. The process of generating test vectors for digital logic using algorithmic based software tools

3. A type of fault model that targets a single gate that is “Slow to Rise” or “Slow to Fall”

4. A term used to describe how effective a vector pattern is at detecting and screening out devices that contain faults

5. Often referred to as Scan Integrity tests, these vectors verify that the Scan chains work properly. they are normally the first Scan tests within a Scan Test Sequence.

6. One of the mandatory IEEE 1149.1 Boundary Scan instructions

7. Test logic contained within the circuit, which generates the input stimulus and captures the output response for testing all or part of a circuit design

8. Phase Shifter circuits, made using XOR gates, generate rotations in the data produced by the Pseudo-Random Pattern Generator. What is another name for this type of circuit?

9. The type of circuit generally used for Output Compression in BIST logic

10. This term referrers to the final compressed test result stored in the MISR, often shifted out to the ATE system for evaluation

12. All IEEE 1149.1 Boundary Scan architectures must incorporate the use of a 24 state machine:
A. True
B. False

13. The Bridge Fault Model works on the assumption that one or more circuit nodes are open:
A. True
B. False

14. In order for ATPG tools to work effectively, the circuit must be:
A. Highly Controllable
B. Highly Observable
C. Mostly combinational logic (limited sequential logic)
D. All of the above

15. “TRST” Test Reset is one of the five mandatory pins associated with the IEEE 1149.1 TAP Controller interface:
A. True
B. False

16. Scan is a design technique that converts sequential logic to combinational logic, enabling ATPG tools to work effectively. This is accomplished by:
A. Converting Normal Flip-Flops to Scan Flops, then chaining the flops together
2. Adding specialized DFT circuitry which converts Normal Flops to XOR gates, then chaining the gates together
3. Converting sequential logic to LFSR (input) and MISR (output) registers

17. During Scan test, the data shift speed should be:
A. 50MHz maximum
B.  At-Speed (the operating speed of the device, or slightly higher if guardbanding)
C. A safe speed
D. 20MHz maximum

18. When implementing an AC Scan test the ideal condition is to set all “Off-Path” signal levels at:
A. Enabling Levels
B. Controlling Levels
C. Quite (calm) Levels
D. Logic One level

19. Functional Launch (LOC) is a Scan test technique that requires two functional clock cycles. Launch on Shift (LOS) is a Scan test technique that requires:
A. No functional clock cycles
B. One functional clock cycle
C. Two functional clock cycles
D. Three functional clock cycles

20.  Iddq is a defect based test, the “q” stands for:
A. Quality
B. Quick
C. Quiescent 

Click Here to Access the Answers

Copyright 1984 - 2007 | Soft Test, Inc. |  All Rights Reserved